The present disclosure relates generally to integrated circuit insulating layers and, more specifically, to an insulating layer having graded densification, an integrated circuit device incorporating the graded insulating layer, and methods of manufacturing the insulating layer.
Metallization of integrated circuits for micro-electronic devices often employs a process generally termed as damascene by which a substrate is inlayed with metal. More specifically, trench and via openings may be formed in one or more insulating layers, lined with a refractory metal cladding or barrier layer, and filled with a bulk interconnect metal. While copper is often employed as the bulk filling interconnect metal, the low resistance of copper can be negated in devices having feature dimensions less than about 0.1 μm. That is, the high-resistance silicon nitride or other refractory metal employed as a barrier layer can result in a significant increase of the total RC time delay, thereby degrading device performance.
Low-k dielectric materials can help reduce the RC time delay and parasitic capacitance, although integration of low-k materials into existing fabrication procedures offers many challenges. For example, low-k materials may rely on the encapsulation of air pockets, bubbles or pores, which can result in a low-k material that is brittle and susceptible to cracking. These porous materials usually undergo a high temperature plasma cure or anneal densification process after deposition to increase the dielectric constant (k). However, after the densification process, or after a subsequent etching process, the low-k insulating layer may have rough surfaces where the pores are exposed. These rough surfaces make subsequent processing difficult, and often result in poor adhesion of subsequently deposited layers. Accordingly, layers formed on or over the low-k insulating layers are susceptible to cracking and peeling, which can increase the dielectric constant of the insulating layers (once again increasing the RC delay) and decrease the conductivity of interconnects formed therein.
Moreover, the high temperature plasma anneal or curing can form a gradient porous layer where pores may be concentrated at the bottom of the insulating layer. Such a gradient porosity can provide weak mechanical stability. As device geometries approach 90 nm and smaller, developing technology includes forming damascene trenches in an insulating layer without employing an etch stop layer, such as by employing a timed etch. However, because the timed etch forms a trench bottom near or within the accumulation of pores near the bottom of the insulating layer, achieving a uniform trench depth profile is difficult, if not impossible, such that the resulting trenches may have rough and jagged bottom surfaces. Again, such rough surfaces do not encourage adequate adhesion of subsequently formed interconnects and other layers, thereby rendering the entire stack of layers susceptible to delaminating, a serious risk to device yield, reliability and performance.
Accordingly, what is needed in the art is an insulating layer and method of manufacture therefore that addresses the problems discussed above.